ELECTRICAL AND ELECTRONICS ENGINEERING-AUG 2K7

Code No: RR12302 Set No. 1
I B.Tech Supplimentary Examinations, Aug/Sep 2007
ELECTRICAL AND ELECTRONICS ENGINEERING
(Bio-Technology)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) State and explain Kirchoff’s Law. [6M]
(b) Calculate the current through the resistance of 5 in the specified direction
as shown in the figure 1b [10M]
Figure 1b
2. (a) Give the constructional features of “CORE” and “Shell” types of transformers,
and give the advantages and disadvantages of each type.
(b) A 5 KVA, 2300 / 230 V, 50 Hz transformer was tested for the iron loss with
normal excitation and copper losses at full load, and these were found to be
40 Watts and 112 Watts respectively. Calculate efficiency of the transformer
at
i. full load.
ii. half full load.
Assume the power factor of the load as 0.8. [8+8]
3. (a) For the network shown in the figure 3(a)i determine the range of RL and IL
that will result in VRL being maintained at 10 V.
i. Determine the maximum Wattage rating of the diode.
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Code No: RR12302 Set No. 1
Figure 3(a)i
ii. The reverse saturation current of the diode is 1 μA. Its peak inverse Volt-
age is 500V. Find ri, Vo that PIV is not exceeded. show in figure 3(a)ii &
figure 3(a)iii
Figure 3(a)ii
Figure 3(a)iii
4. (a) The half wave rectifier shown in the figure 4a is fed with a sinusoidal voltage
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Code No: RR12302 Set No. 1
V=20 sin100t.
i. Sketch the output waveform.
ii. Determine the DC output voltage assuming ideal diode behaviour.
iii. Repeat the calculations assuming the simplified diode (silicon) model.
Figure 4a
(b) Draw the circuit diagram of full wave rectifier having two diodes and explain
its operation. [8+8]
5. (a) Draw the circuit of transistor (p-n-p) in the CE configuration, sketch the
family of input and output characteristics and explain the shape of the curves
qualitatively.
(b) For the circuit in figure 5b shown find R. Neglect the reverse saturation current.
Assume silicon transistor is used.
[8+8]
Figure 5b
6. (a) Draw the circuit of a transformer coupled amplifier and explain its operations.
(b) Draw the circuit of a class B push-pull amplifier and derive expression for the
output power. [8+8]
7. (a) Explain the operation of an integrator using OP-AMPs.
(b) Distinguish between positive and negative feedbacks.
(c) List out the characteristics of OP-AMP. [6+4+6]
8. (a) Explain the principle of Half-adder. Draw various implementations of sum
and carry of Half-adder.
(b) Implement AND and OR gate using discrete components.
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Code No: RR12302 Set No. 1
(c) How do you convert JK-flip-flop to T and D flip-flops. . [6+6+4]
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Code No: RR12302 Set No. 2
I B.Tech Supplimentary Examinations, Aug/Sep 2007
ELECTRICAL AND ELECTRONICS ENGINEERING
(Bio-Technology)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆ ⋆ ⋆ ⋆ ⋆
1. (a) Derive the voltage current relations (between line and phase) values for a star
and delta connected systems.
(b) A 3-phase, 4 wire 208V system supplies power to a star connected load each
arm with impedance equal to (17.32 − j10) ohms (per phase) find the line
currents, power consumed, and the power factor of the load. [8+8]
2. (a) Explain the constructional details of a synchronous machine giving the reasons
for making two types of rotors.
(b) Explain auxiliary motor starting of synchronous motors. [6+10]
3. (a) Draw the V-I characteristics of Zener diode and explain.
(b) For the Zener voltage regulator shown in the figure 3b determine the range
of RL and IL that gives a stabilized voltage of 10 V. What should be wattage
rating of the diode?
Figure 3b
(c) Explain how Zener diode acts as voltage regulator. [4+8+4]
4. (a) The half wave rectifier shown in the figure 4a is fed with a sinusoidal voltage
V=20 sin100t.
i. Sketch the output waveform.
ii. Determine the DC output voltage assuming ideal diode behaviour.
iii. Repeat the calculations assuming the simplified diode (silicon) model.
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Code No: RR12302 Set No. 2
Figure 4a
(b) Draw the circuit diagram of full wave rectifier having two diodes and explain
its operation. [8+8]
5. (a) Compare the merits and drawbacks of FET and BJT.
(b) Sketch the basic structure of an n-channel JFET.
(c) Define the pinch off voltage VP and sketch the depletion region before and
after pinch-off and explain the reason. [6+4+6]
6. (a) Give the advantages of negative feedback amplifier.
(b) Draw the circuit of a voltage shunt feedback amplifier and explain.
(c) When the negative feedback is applied to an amplifier of gain 100, the overall
gain falls to 50. Calculate
i. the feedback factor ’β’
ii. If the same feedback factor is maintained, find the value of amplifier gain
required if the overall gain is to be 75. [4+6+6]
7. (a) With the help of neat circuit diagram, explain the following applications of
OP-AMP
i. Multiplier
ii. differentiator
iii. Subtractor.
(b) Design a scaling adder circuit using OP-AMP, to give the output voltage
Vo = −(3V 1 +4V 2 +5V 3),where V1, V2 and V3 are the input voltages given to
the circuit. [10+6]
8. (a) Realize NAND gate using minimum number of NOR gates.
(b) Explain the principle of basic shift registers.
(c) Distinguish between asynchronous and synchronous counters.
(d) Distinguish between Ring and Twisted Ring counters. [4+4+4+4]
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Code No: RR12302 Set No. 3
I B.Tech Supplimentary Examinations, Aug/Sep 2007
ELECTRICAL AND ELECTRONICS ENGINEERING
(Bio-Technology)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆ ⋆ ⋆ ⋆ ⋆
1. (a) Derive an equation for the total power consumed in a three ? phase circuit.
Will it depend on the type of load connected?
(b) Three identical impedances 106 53.10 ohm are connected in delta to a 3-phase,
240 volt balanced supply. Find the line currents and power consumed. [8+8]
2. (a) Give the various power stages of a 3-phase induction motor(the various stages
from the input to induction motor to output) and explain each stage.
(b) Explain principle of operation of three − phase induction motor. [8+8]
3. (a) Give the specifications of Zener diode.
(b) Explain the terms:
i. Space-charge region
ii. Transition region.
iii. Barrier potential.
iv. Donar impurities,
v. Acceptor impurities. [4+12]
4. (a) The half wave rectifier shown in the figure 4a is fed with a sinusoidal voltage
V=20 sin100t.
i. Sketch the output waveform.
ii. Determine the DC output voltage assuming ideal diode behaviour.
iii. Repeat the calculations assuming the simplified diode (silicon) model.
Figure 4a
(b) Draw the circuit diagram of full wave rectifier having two diodes and explain
its operation. [8+8]
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Code No: RR12302 Set No. 3
5. (a) Draw the circuit of transistor (p-n-p) in the CE configuration, sketch the
family of input and output characteristics and explain the shape of the curves
qualitatively.
(b) For the circuit in figure 5b shown find R. Neglect the reverse saturation current.
Assume silicon transistor is used.
[8+8]
Figure 5b
6. (a) Draw the h-parameter small signal low-frequency BJT model and what are
the dimensions of each parameter.
(b) Draw the approximate h-parameter model for common collector configuration
and derive expressions for current gain, Input Resistance, voltage gain and
output resistance. [6+10]
7. (a) Draw the circuit diagram of Wien bridge oscillator using BJT. Show that the
gain of the amplifier must be at least 3 for the oscillations to occur.
(b) For the fixed-bias Ge transistor, n-p-n type, the junction voltages at satura-
tion and cutoff one in active region, may be assumed to zero. This circuit
operate properly over the temperature range -50 oC to 75 oC and to just start
malfunctioning at these extremes. The various circuit specifications are: VCC
= 4.5V, VBB = 3volts, hfe=40 at -50 oC, and hfe=60 at 75 oC, ICBO = 4
μA at 25 oC and doubles every 10 oC. Collector current is 10 μA. Design the
values of Rc1, R1 and R2. [8+8]
8. (a) Explain the following switching circuit in binary logic notation as shown in
the figure8a
Figure 8a
(b) Define a register. Construct a shift register using S-R flip-flops and explain
its operation.
(c) Convert the following numbers:
i. (101101. 101101)2 decimal number
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Code No: RR12302 Set No. 3
ii. (5345)10 to binary number. [4+6+6]
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Code No: RR12302 Set No. 4
I B.Tech Supplimentary Examinations, Aug/Sep 2007
ELECTRICAL AND ELECTRONICS ENGINEERING
(Bio-Technology)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆ ⋆ ⋆ ⋆ ⋆
1. (a) Define resistance.
(b) State and explain Ohms Law.
(c) Find out the equivalent resistance of the following circuit between the points
A and B (all values are in ohms) as shown in the figure 1c [2+4+4]
Figure 1c
(d) Find the impedance between ‘X’ and ‘Y’ points of the figure 1d shown. [6]
Figure 1d
2. (a) Discuss the classification of D.C generators with suitable diagrams, and give
the practical applications of each generator.
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Code No: RR12302 Set No. 4
(b) A 10 kW shunt generator supplies load at a terminal voltage of 200 volts.
The shunt field resistance is 100 ohms and armature resistance is 0.1 ohm.
Calculate the e.m.f induced in the generator. [8+8]
3. (a) For the network shown in the figure 3(a)i determine the range of RL and IL
that will result in VRL being maintained at 10 V.
i. Determine the maximum Wattage rating of the diode.
Figure 3(a)i
ii. The reverse saturation current of the diode is 1 μA. Its peak inverse Volt-
age is 500V. Find ri, Vo that PIV is not exceeded. show in figure 3(a)ii &
figure 3(a)iii
Figure 3(a)ii
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Code No: RR12302 Set No. 4
Figure 3(a)iii
4. (a) Draw the circuit diagram of half wave rectifier and explain its operation.
(b) A half wave rectifier is fed by 220 V, 50 Hz via a step down transformer of
turns ratio 11:1 find
i. the output DC and
ii. peak inverse voltage under no load condition. [8+8]
5. (a) Sketch a family of drain characteristics of JFET and explain the shape of the
curves qualitatively.
(b) Obtain transfer characteristic of JFET from its drain characteristics and ex-
plain the shape of curves qualitatively.
(c) How a JFET can be used as voltage variable resistor (VVR)? Explain.[4+6+6]
6. (a) Compare the three transistor amplifier configurations with related to AI , Av,
Ri and R0.
(b) For the circuit shown calculate AI , AV , Ri and R0 using approximate
h-parameter model. Assume hfe = 50, hie = 1100 , hoe = 25 μA/V, hre =
2.5 × 10−4 as shown in the figure 6b.
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Code No: RR12302 Set No. 4
Figure 6b
7. (a) Explain the principle of operation of self-bias binary circuit.
(b) A FET phase shift oscillator has gm=500 μs, and rd = 30 k. The feedback
resistance is 100 k, and the capacitor value is 64.97 pF. Calculate the fre-
quency of oscillations and the value of RD. Draw the corresponding circuit
diagram.
[8+8]
8. (a) Realize Exclusive OR gate using minimum number of NAND gates.
(b) Realize SR flip-flop using NAND gates.
(c) Explain the principle of decade counter and realize it using JK-flip-flops.
(d) Realize exclusive OR gate using basic gates. [4+4+4+4]
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